The present invention relates generally to integrated circuits, and more particularly, to a control system for waking up a circuit from a sleep or low power mode.
Integrated circuits (IC) include power supplies that provide different supply voltages to internal circuits. ICs often operate in different power modes including RUN, STOP, and STANDBY modes. The RUN mode is a high power mode and the STOP and STANDBY modes are low power modes. A power supply further provides voltage regulation and includes a high power regulator (HPREG) for regulating the supply voltage during the RUN mode, a low power regulator (LPREG) for regulating the supply voltage during the STOP mode, and an ultra low power regulator (ULPREG) for regulating the supply voltage during the STANDBY mode.
Based on the mode of operation, the electrical components within an IC may be categorized as first and second sets of circuits. The first set of circuits includes core functional elements of the IC such as processors, memories and interface circuits and often occupies the majority of the IC area (up to 99% in many ICs). The first set of circuits is active when the IC is in the high power mode. The second set of circuits includes circuits that maintain basic timer functions, random access memory (RAM) and a wake-up state machine and occupies relatively lesser area (around 1%) of the IC. The second set of circuits is active throughout the operation of the IC, regardless of the mode of operation of the IC.
The first and second sets of circuits both operate on a regulated supply voltage received from the HPREG when the IC in the RUN mode, while the second set of circuits operates on a regulated supply voltage received from the LPREG and ULPREG when the IC is in the STOP and STANDBY modes, respectively.
The wake-up state machine operates on a clock signal and generates control signals for enabling transition of the IC from the low power mode to the high power mode. The higher the frequency of the clock signal, the faster the transition of the IC from the low power mode to the high power mode. However, a high frequency clock source consumes high power and draws a large current from the LPREG/ULPREG during transition of the IC from the low to high power mode.
The LPREG/ULPREG is designed for sustaining a low order current and often fails to sustain an increased current requirement of the high frequency clock source. When the IC wakes up from the low power mode, a sudden change in current load can create a low voltage event and cause the IC to undergo reset. A re-boot of the IC can affect the system state and may lead to loss of critical data and time. In systems such as automotive systems, system state is very important so it is preferred not to lose state due to frequent resets. A low frequency clock source prevents the IC from reset, however, it increases the overall time (wake-up time) taken by the IC to exit the low power mode and enter the high power mode, and also affects overall system performance.
An alternate way to prevent IC reset is to mask low voltage reset when the IC wakes up. However, this may result in masking low voltage conditions that occur due to conditions other than exit from low power mode, thereby causing the IC to function unreliably. Another way to prevent reset is to use a low power regulator that can sustain high current requirements of the high frequency clock source. However, using such a regulator may lead to high power loss in low power modes.
Therefore, there is a need for a wake-up control system that prevents an IC from a reset caused by increased load currents when the IC wakes up and transitions from low power mode to high power mode, and that overcomes the above-mentioned limitations of existing wake-up control systems.